Notes from the 2017 Packaging and Testing Annual Meeting: Advanced Packaging in the Internet of Things Era

It has been a month since the 2017 China Semiconductor Packaging, Testing Technology and Market Annual Conference, but the semiconductor industry, which requires a lot of accumulation, does not need to focus on hot topics. One month later, the wonderful speeches of the experts at the annual conference are still lingering in the air. . In addition to the keyword "packaging and testing", the most mentioned keyword by the guests is "Internet of Things". Therefore, after sorting out the opinions of the guests at the annual meeting, let us think about advanced packaging in the era of the Internet of Things.

The growth rate of smartphones has slowed down

The driving force of the semiconductor downstream market has gone through several stages. First, it was personal computers with shipments of 100 million units, and later it became ten million units. There are billions of mobile phone terminals and communication products. Since 2010, smart mobile terminals represented by smartphones have set off the climax of the mobile Internet and become the latest killer application. Looking back on the past two or three decades, killer applications in the downstream electronics industry have greatly boosted the development of the semiconductor industry, constantly motivating semiconductor manufacturers to expand production capacity and improve performance. As semiconductor production increases, semiconductor prices also fall quickly, making them cheaper and more cost-effective. High-performance semiconductor devices in turn promote the accelerated development of the electronics industry. The semiconductor industry and the electronics industry encourage each other, forming a good positive feedback. But at present, the penetration rate of smartphones is already very high and the market growth rate is beginning to slow down. What will be the next killer application?

The Internet of Things may become the next killer application

According to IHS predictions, the number of IoT node connections will reach 70 billion in 2025.

From a quantitative point of view, the Internet of Things has left billions of mobile phone terminal products far behind, and is likely to become the next wave of killer applications. But the problem with the Internet of Things is that the products are diversified and the applications are very scattered. The market we face is changing from a single homogeneous large-scale market to a small-scale heterogeneous market. For an industry that relies on volume such as semiconductors, the initial investment in chip design and tape-out is huge. Without volume, economies of scale cannot be produced, and the amortized cost per chip is very high.

In addition to meeting the challenges of small-scale heterogeneity, the key elements required for the Internet of Things also include: diverse sensors (various sensors and Sensor Hub), distributed computing capabilities (cloud computing and edge computing) , flexible connectivity capabilities (5G, WIFI, NB-IOT, Lora, Bluetooth, NFC, M2M...), storage capabilities (memory and data center) and network security. These key elements will stimulate the development of CPU/AP/GPU, SSD/Memory, biometric chips, wireless communication devices, sensors, storage devices and power devices.

The diverse downstream products of the Internet of Things put forward more requirements for packaging

The diversity of Internet of Things products means that chip manufacturing will shift from simply pursuing the advancement of process technology to pursuing both The advanced nature of the manufacturing process also requires the breadth of the product line. The possible trends of chips in the Internet of Things era are: small package, high performance, low power consumption, low cost, heterogeneous integration (Stacking, Double Side, EMI Shielding, Antenna...).

Packaging requirements for automotive electronics: The current hot spots in automotive electronics are ADAS systems and driverless AI deep learning. Global automobile production and sales in 2016 were approximately 80 million units, of which 28 million were produced and sold in the Chinese market, providing a large enough stage for automotive electronics. ADAS automotive systems have broad development prospects. For safety reasons, the U.S. NHTSA requires that cars produced from May 2018 onwards must be equipped with a reversing image display system. In addition, the lane departure warning system (LDW), forward collision warning system (FCW), automatic emergency braking system (AEBS), vehicle distance control system (ACC), and night vision system (NV) markets are also growing rapidly. The increasingly stringent traffic regulations in China's first- and second-tier cities have also increased people's demand for automotive electronic systems such as ADAS.

ADAS, autonomous driving, artificial intelligence, and deep learning have high requirements for real-time data processing, so the chip is required to achieve ultra-high computing performance. In addition, there are also requirements for miniaturized design and heat dissipation of chips and modules. Future automotive electronic chips may require Use 2.5D technology for heterogeneous integration, such as integrating CPU, GPU, FPGA, and DRAM into one package.

Packaging requirements for personal mobile terminals: The personal consumer electronics market will also continue to grow steadily. The main demands of personal consumer electronics equipment are miniaturization, power saving, high integration, low cost and modularity. For example, personal mobile terminals are required to be modularized with multiple functions, integrating application processor modules, baseband modules, radio frequency modules, fingerprint identification modules, communication modules, power management modules, etc. The requirements for chip packaging form of these products are also miniaturization, power saving, high integration, and modularity. The chip packaging forms are mainly "Stack Die on Passive", "Antenna in SiP", "Double Side SiP", etc. For example, Apple's 3D SiP integrated packaging technology has developed from the past ePOP & BD PoP to the current HBW-PoP and FO-PoP. The next generation mobile terminal packaging form may be FO-PoP plus FO-MCM. This packaging form Able to provide thinner designs.

Packaging requirements for 5G network chips: The construction of 5G networks and NB-IOT networks based on the Internet of Things means that the network chip market will perform well. Big data, cloud computing and data centers have a very large demand for memory chips and FPGA GPU/CPUs. Communication network chips are characterized by large scale, high performance and low power consumption. In addition, intellectual property (IP) cores are complex and Yield, etc. are all important issues faced by manufacturers. These demands and problems have also prompted the development of network chip packaging from bumping & FC to 2.5D, FO-MCM and 3D, and the successful commercialization of TSV technology has enabled chip stacking packaging technology. Making substantial progress, Hynix and Samsung have successfully developed 3D stacked packaging high-bandwidth memory (HBM), and Micron and Intel are also jointly promoting the research and development of stacked packaging hybrid memory cubes (HMC). In the field of chip design, BROADCOM, Companies such as GLOBAL FOUNDRIES have also successfully introduced TSV technology and are now able to provide 2.5D stacking back-end design services for communication network chips

The impact of the upstream wafer foundry supply side on packaging

On the one hand, the demand in the downstream market is very strong. On the other hand, capital led by large funds continues to invest heavily in the wafer foundry manufacturing industry, causing upstream manufacturing to expand production capacity. According to SEMI estimates, the world will By 2020, 62 semiconductor wafer fabs will be put into operation, 26 of which are in mainland China, accounting for 42% of the global total. Currently, wafer fabs are still mainly based on mature processes above 40nm, accounting for 42% of the total wafer fabs. 60 of the foundry output value. In the future, the automotive electronics, consumer electronics and network communications industries will have higher and higher requirements for chip integration, functionality and performance. Mainstream wafer factories SMIC and UMC are developing 28nm processes, among which TSMC 28nm The mass production of the process has entered its fifth year, and has even entered the 10Xnm process.

As the wafer technology node continues to approach the atomic level, how to continue Moore's Law may not be possible? When considering wafer manufacturing, we should also consider issues from the entire industry chain of the chip manufacturing process. System-level optimization is required from chip design, wafer manufacturing to packaging and testing. Therefore, wafer manufacturing, chip packaging and testing, and system integration are required. The boundaries between the three will become increasingly blurred. First, there are more and more subsystems appearing between chip packaging and testing and system integration. Various system-in-package SiPs require chips with different processes and functions to be packaged together using 3D and other methods, which not only reduces the size, but also It also improves system integration capabilities.

Panel board-level packaging will also reduce packaging costs on a large scale and improve labor productivity. Secondly, fan-in and fan-out wafer-level packaging have emerged between chip manufacturing and chip packaging and testing. FO-WLP packaging has the characteristics of ultra-thin and high I/O pin count. It is the third packaging after wire bonding and flip chip. One of the three generations of packaging technology, the final chip product has the advantages of small size, low cost, good heat dissipation, excellent electrical performance, and high reliability.

The development status of advanced packaging

Advanced packaging forms are increasingly used in China, and the market share of traditional TO and DIP packaging types has been less than 20%.

In recent years, the industry’s advanced packaging technologies include 2.1D, 3D packaging, Fan Out WLP, WLCSP, SIP and TSV, represented by wafer level packaging (WLCSP) and carrier level packaging (PLP).

Before 2013, 2.5D TSV packaging technology was mainly used for integration between logic modules and packaging of FPGA chips and other products, with a low degree of integration. In 2014, some of the industry's 3D TSV packaging technology has been used in memory chips and high-performance chip packaging, such as large-capacity memory chip stacking. In 2015, 2.5D TSV technology began to be used in some high-end GPU/CPU, network chips, and processor (AP) memory integrated chips. 3D packaging has more advantages in terms of integration, performance, power consumption, smaller size, design freedom, and development time. At the same time, it has higher design freedom and shorter development time. It is one of the most promising packaging technologies. kind. It is widely used in high-end mobile phone chips, large-scale I/O chips and high-performance chips. For example, an MCU plus a SiP reduces the original size by 80%.

At present, the advanced packaging capabilities of domestic leading packaging and testing companies have been initially formed

At the 2017 Semiconductor Packaging and Testing Annual Conference, Chairman Wang Xinchao of Changdian Technology expressed his views on the current capabilities of Chinese packaging and testing manufacturers. The level of advanced packaging technology also mentioned three points:

SiP system-level packaging: At present, the SiP module with the highest level of integration and precision has achieved large-scale mass production at Changdian Technology; Huatian Technology’s TSV SiP Fingerprint recognition packaging products have been successfully used in Huawei series mobile phones.

WLP wafer-level packaging: Changdian Technology’s Fan Out wafer-level packaging has shipped more than 1.5 billion units, and its wholly-owned subsidiary Changdian Advanced has become the world’s largest integrated circuit Fan -In one of the WLCSP packaging bases; Jingfang Technology has become one of the world's largest WLP wafer-level packaging bases for image sensors.

FC flip-chip packaging: Through cross-border mergers and acquisitions, leading domestic companies have acquired internationally advanced FC flip-chip packaging technology, such as Changdian Technology’s FC-POP packaging technology for smartphone processors; Tongfu Microelectronics’ high-pin-count FC-BGA packaging technology; the three major domestic packaging and testing factories have also basically mastered the 16/14nm FC flip-chip packaging technology.