What does the general company take in the written recruitment test?

What are the contents of analog circuit 1 and Kirchhoff theorem? Kirchhoff's current law is a law of charge conservation, that is, the charge flowing into a node in a circuit is equal to the charge flowing out of the same node. Kirchhoff's voltage law is the law of conservation of energy, that is, the sum of loop voltages in the circuit is 0.2, and the plate capacitance formula (C=εS/4πkd). (unknown) 3, the most basic such as triode curve characteristics. (unknown) 4. Describe the concept of feedback circuits and list their applications. (Shi Lan Microelectronics Company). Types of negative feedback (voltage parallel feedback, current series feedback, voltage series feedback and current parallel feedback); Advantages of negative feedback (reducing the gain sensitivity of the amplifier, changing the input resistance and output resistance, improving the linear and nonlinear distortion of the amplifier, effectively expanding the passband of the amplifier, and automatically adjusting the function) (unknown) 6. What is the purpose of frequency compensation of the amplifier circuit and what are the methods? (Shi Lan Microelectronics Company). Frequency response, such as how to stabilize and how to change the frequency response curve. (unknown) 8. This paper gives an operational amplifier, how to compensate the phase, and draws the compensated Porter diagram. (concave and convex) 9. Types of basic amplifier circuits (voltage amplifier, current amplifier, transconductance amplifier and transimpedance amplifier), advantages and disadvantages, especially the reason why differential structure is widely used. (unknown) 10. Give a differential channel, tell its output voltages Y+ and Y-, and find the * * * mode component and the differential mode component. (unknown) 1 1, two input tubes of the differential amplifier. (concave and convex) 12. Draw the circuit schematic diagram of addition, subtraction, differentiation and integration operations composed of operational amplifiers. And draw the transistor-level operational amplifier circuit. (Shi Lan Microelectronics) 13. 10 times amplifier consists of operational amplifier. (unknown) 14. Take a simple circuit, which allows you to analyze the characteristics of the output voltage (i.e. the integrating circuit) and find the rise/fall time of a certain point at the output end. (15, resistor R and capacitor C are connected in series, the input voltage is between R and C, and the output voltage is above C and above R respectively. It is necessary to determine the frequency spectrum of the input voltage of these two circuits and what high-pass filters and low-pass filters these two circuits are. When RC; Q and clock delay, write out the factors that determine the maximum clock, and give the expression at the same time. (VIA 2003. 1 1.06 Shanghai written test questions) 18, talk about the advantages and disadvantages of static and dynamic time series simulation. (VIA 2003. 1 1.06 Shanghai written test questions) 19, a four-level Mux, in which the second-level signal is how to improve the timing of key signals. (VIA2003. 1 1.06 Shanghai written test questions) 20. Give a gate-level diagram, give each gate the transmission delay, ask what the critical path is, and give the input, so that the output depends on the critical path. 2 1, Karnaugh map simplification of digital circuit in logic, timing (synchronous asynchronous difference), several flip-flops (difference, advantages), full adder and so on. (unknown) 22. Karnaugh map writes logical expressions. (VIA 2003. 1 1.06 Shanghai written test questions) 23. Simplified F (A, b, c, D) = m (1, 3, 4, 5, 10,1. (VIA) 24。 Please show the schematic diagram, layout and cross section of CMOS inverter by Pwell process. Draw its transfer curve (Vout-Vin) and explain the PMOS and NMOS working areas of each section of the transfer curve. (Test the circuit design by pen-Beijing -03. 1 1.09) 25. To design a CMOS inverter with balanced rise and fall time, please define the rationalization of channel widths of PMOS and NMOS and explain? 26. Why is the aspect ratio of P tube in standard inverter greater than that of N tube? (Shi Lan Microelectronics Company) Construct a dual-input NAND gate with mos transistor. 28. Please draw a schematic diagram of converter level of CMOS 2 input AND gate, and explain which input responds faster to the rising edge of output. (less delay time e). (Circuit Design-Beijing -03. 1 1.09) 29. Draw NOT, NAND, NOR symbols, truth tables, and transistor-level circuits. (Infineon written test) 30. Draw a picture of CMOS, and draw an alternative mux gate. (VIA 2003. 1 1.06 Shanghai written test questions) 3 1, XOR with a binary mux and an inv. (Philips-Datang written test) 32. Draw a cmos circuit diagram of Y = A * B+C (scientific and optical test questions) 33. Using logic and cmos circuit to realize ab+cd. (Philips-Datang written test) 34. Draw the transistor-level circuit diagram of CMOS circuit and realize Y=A*B+C(D+E). (Shi Lan Microelectronics Company) F(x, y, z)=xz+yz' is realized by 1 (unknown) 36. Give an expression f = xxxx+xxxx+xxxx+xxxx with the least number of NAND gates (actually simplified) 37. A simple schematic diagram composed of many NOT, NOT, NAND and NOR is given, and the waveforms of each point are drawn according to the input waveform. (Infineon written test) 38. To realize logic (A XOR B) or (c and d), please choose one of the following logics and explain the reason. 1) inv 2) and 3) or 4) NAND 5) nor 6) xor answer: NAND (unknown) 39. Design of full adder with NAND gate. (Huawei) 40. Give you two gate circuits to analyze the similarities and differences. (Huawei) 4 1, which is realized by a simple circuit. When A is the input, the output B waveform is ... (Shi Lan Microelectronics) 42, A, B, C, D and E to vote, and the majority is subordinate to the minority, and the output is F (that is, if the number of 1 in A, B, C, D and E is greater than 0, The function of D flip-flop is represented by waveform. (Yang Zhi electronic written test) 44. Constructing edge flip-flops with transmission gates and inverters. (Yang Zhi electronic written test) 45 points. Draw a d trigger with logic. (VIA 2003. 1 1.06 Shanghai written test questions) 46. Draw the structure diagram of DFF and realize it with verilog. (VIA) 47。 Draw the circuit diagram and layout of CMOS D latch. (unknown) 48. The difference between d flip-flop and d latch. (Xintai Hardware Interview) 49. Briefly describe the similarities and differences between latch and filp-flop. The concepts and differences of (unknown) 50, LATCH and DFF. (unknown) 5 1, the difference between latch and register, why register is used more now. The behavior level describes how latch came into being. (Nanshan Bridge) 52. Make a binary circuit with D flip-flop and ask what the state diagram is. (Huawei) 53. Please draw a logic circuit that uses D flip-flop to realize 2 times frequency division? (Hanwang written test) 54. How to form a divide-by-two circuit with D flip-flop and NOR gate? (Eastcom written test) 55. 16 How many flip-flop circuits do you need? (Intel) 16 frequency division? 56. Design a 1 bit adder with flip-flop and logic gate, input carry and current stage, and output carry and next stage. (unknown) 57. Quaternary counting with d flip-flop. (Huawei) 58. Realize n-bit Johnson counter, N=5. (Nanshan Bridge) 59. Design a hexadecimal cycle counter with preset initial value in a familiar design way. 15? (Shi Lan Microelectronics Company) Of course, you must ask Verilog/VHDL for digital circuit design, such as designing counters. The difference between (unknown) 6 1 and blocking non-blocking assignment. (Nanshan Bridge) 62. Write the verilog module of asynchronous d flip-flop. Module dff8 (clock, reset, d, q); Input clk input reset; Enter [7: 0] d; Output [7: 0] q; reg[7:0]q； Always @ (posedgclk or posedgeset) if (reset) q <; = 0; else q & lt= d； Endmodule 63, using D flip-flop to realize Verilog description of 2 times frequency division? (Hanwang written test) module divide2( clk, clk_o, reset); Input clk, reset; Output clk _ o；; Wires come in; Sign out; If (reset) out <: = 0; Else out < = in assignment in = ~ out assignment clk _ o = out terminal module 64. Programmable logic devices are becoming more and more important in modern electronic design. Excuse me: a) What programmable logic devices do you know? B) Try VHDL or VERILOG and be able to describe the logic of 8-bit D flip-flop. (Hanwang written test) PAL, PLD, CPLD, FPGA. Module dff8 (clock, reset, d, q); Input clk input reset; Enter d; Output q; reg q； Always @ (posedgclk or posedgeset) if (reset) q <; = 0; else q & lt= d； Endmodule 65, please describe the four-bit full adder and the divide-by-5 circuit with HDL. (Shi Lan Microelectronics Company) Write a code with VERILOG or VHDL to realize 10 binary counter. (unknown) 67. Write code with VERILOG or VHDL to eliminate faults. (unknown) 68. The topic of a state machine is realized by verilog (but this state machine is really poorly drawn and easily misunderstood). (VIA 2003. 1 1.06 Shanghai written test questions) 69. Describe the design of traffic lights. (Shi Lan Microelectronics Company) Drawing state machine, accepting 1, 2,5 cents newspaper vending machine, 5 cents for each newspaper. (yangzhi electronic written test) 7 1. Design a vending machine system. Soda sellers can only put three kinds of coins, so change them correctly. (1) Draw fsm (finite state machine); (2) Programming with verilog, and the syntax should meet the requirements of fpga design. () 72. Design an automatic beverage vending machine. Drinks have 10 cents, coins have 5 cents, and coins have 10 cents. Consider the change: (1) Draw fsm (finite state machine); (2) Programming with verilog, and the syntax should meet the requirements of fpga design; (3) Tools that can be used in the design project and general design process. (unknown) 73. Draw a state diagram that can detect 100 10 string, and realize it with verilog. (VIA) 74。 The sequence detection module of101101is implemented by finite state machine. (Nanshan Bridge) A is the input end and B is the output end. If the continuous input of A is 1 10 1, the output of B is 1, otherwise it is 0. For example, a: 00011001010010011. Please describe its state machine with RTL. (unknown) 75. Use verilog/vddl to detect a specific string in the stream (written by the state machine in different states). (Philips-Datang written test) 76. Write a fifo controller (including empty, full and half-full signals) with verilog/vhdl. (Philips-Datang written test) 77. An existing user needs an integrated circuit product and requires the following functions: y=lnx, where x is a 4-bit binary integer input signal. Y is a binary decimal output, requiring two decimal places. The power supply voltage is 3~5v. After the company receives this project, you are responsible for the design of this product and try to discuss the whole design process of this product. (Shi Lan Microelectronics Company) What's the difference between sram, falsh memory and dram? (Xintai Hardware Interview) 79. Give the schematic diagram of single-tube DRAM (Yang Songhua and Feng Maoguan, basic authors of digital electronic technology, Xidian Edition, page 205, Figure 9- 14b), and ask if there are any methods to improve the refresh time. There are always five questions that I can't remember. (Reduce the temperature and increase the storage capacity of the capacitor) (Infineon written test) 80. Please draw a schematic diagram of an ordinary SRAM cell with six transistors, and point out which node can store data and which node is controlled by word lines. (VIA pen test circuit design-Beijing-03.11.09) 81,nouns: sram, ssram, sdram nouns IRQ, BIOS, USB, VHDL, SDR IRQ: interrupt request BIOS: basic input and output system USB: universal serial bus VHDL: VHIC. English abbreviation for Dynamic Random Access Memory (DRAM). Nouns are just boring abbreviations in foreign languages, such as PCI, ECC, DDR, interrupt, Pipeline IRQ, BIOS, USB, VHDL, VLSI VCO (Voltage Controlled Oscillator) RAM (Dynamic Random Access Memory), FIR IIR DFT (Discrete Fourier Transform) or Chinese. For example: A. Quantization error B. Histogram C. White balance _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.