Dear, why is this verilog program stuck in the simulation? I just can't get the waveform. Compile and start the simulation.

The always @ (posedgclk) block contains a for loop?

Verilog is different from software, so it cannot be integrated into hardware implementation.

Grammatically, when the rising edge of clock clk comes, as long as year _ s _ in >；; 0, which is continuously assigned to year _ s.

Endless cycle, right? Do you want to count it all in one clock?

Always @ (posedgclk) usually synthesizes registers, but registers can only be assigned once per clock, and they have to be assigned multiple times, and the last assignment will also cover the previous assignment, so it can only be implemented in multiple cycles.

Instead of for, you can use the serial input year_s_in, sample with the rising edge of clk, and then judge that it is calculated once every clock.