Is the CPU body (quality) better near the center of the wafer?

At least lithography is different. But the difference is not big (all within the tolerance range). If the difference is too big to affect the cpu system, stop the machine and check it early. Fab materials, labor and time are extremely expensive, and this will never happen. At the same time, other links will correct the deviation caused by lithography. The tolerance of many lithography links is related to the error correction ability of other links. So in general, physical fitness has a slight impact, but it is not something that ordinary players need to worry about. The difference between detail lithography: vertical: in big data, the image near the center of the circle is better focused than the edge. So the lines carved on this layer are clear. Don't think that the image is scanned line by line, just because the focus is the same. In fact, there are too many factors, and human beings have tried their best to overcome those known influences. Edge effect is everywhere, and the center sweetness of watermelon is not white sweetness. For example, a country's high-end mask aligner silicon wafer is attracted to the silicon platform, and the stress on the edge and center is different. When the edge of the silicon wafer is enlarged, it is actually tilted ... the vertical focus on the edge has silently shed tears.

Horizontal: The standard deviation of image alignment near the center of the circle is better than that near the edge. Generally, a cpu has to undergo at least ten to dozens of photoetching. I'm not afraid of my floor. I carved it off-center because the next floor is the same and still valid. But I'm afraid there is a relative deviation between these two floors. The smaller the standard deviation, the more accurate it is. For example, mask aligner, as a CPU, should be high-end, and the high-end should be immersive. The immersion liquid is easier to stay at the edge, so it needs to be evaporated. If it evaporates, it will cool down, and if it cools down, it will cause the silicon wafer to deform. If it is deformed, horizontal alignment is not allowed.