What is the principle of memory?

Memory tells the working principle and function.

introduce

Memory is a storage device used to save information in modern information technology. Its concept is very broad and there are many levels. In a digital system, as long as it can store binary data, it can be memory. In integrated circuits, circuits with storage function without physical form are also called memories, such as RAM and FIFO. In the system, physical storage devices are also called memories, such as memory chips and TF cards. All the information in the computer, including the input raw data, computer programs, intermediate running results and final running results, are stored in the memory. It stores and retrieves information according to the location specified by the controller. With the memory, the computer has the memory function, which ensures the normal work. Memory in a computer can be divided into main memory (internal memory) and auxiliary memory (external memory), and there are also classification methods of external memory and internal memory. External memory is usually a magnetic medium or an optical disk, which can store information for a long time. Memory refers to the storage component on the motherboard, which is used to store the data and programs currently being executed, but only for temporary storage of programs and data. When the power supply is turned off or power is cut off, data will be lost.

The main function of memory is to store programs and various data, and it can automatically access programs or data at high speed during computer operation. Memory is a device with "memory" function, which uses physical devices with two stable states to store information. These devices are also called memory elements. In a computer, only two digits "0" and "1" are used to represent data.

The two stable states of the storage element are "0" and "1" respectively. Decimal numbers used in daily life must be converted into equivalent binary numbers before they can be stored in memory. Various characters processed in a computer, such as English letters and operation symbols, must be converted into binary codes before they can be stored and operated.

Memory: Device memory bits used for storing programs and data: memory cells used for storing binary bits are the smallest memory units, or called memory cell memory words: when a number (n-bit binary bits) is stored or taken out as a whole, it is called memory cells: several memory cells storing a memory word form a memory cell library; a large number of memory cells form a memory cell library; Memory cell address: the address of the digital word of the memory cell.

A memory integrated circuit is formed with a memory bank (an array consisting of a large number of memory cells) as the core and necessary address decoding and read-write control circuits. Coupled with the necessary I/O interface and some additional circuits such as access policy management, a memory chip such as that commonly used in mobile phones is formed. Due to the new integrated circuit manufacturing or chip packaging technology, DRAM and flash memory cells can now be integrated into a single chip. Memory chip, control chip (responsible for complex access control, storage management, encryption, cooperation with other devices, etc.). ) and clock, power supply and other necessary components are integrated on the circuit board to form a complete machine, which is a storage product, such as a U disk. From memory cells (transistor arrays) to memory integrated circuits and then to memory devices, information is stored, with different levels.

A storage medium that constitutes a memory, a storage element that can store binary codes. A memory cell is composed of several memory elements, and then a memory is composed of many memory cells. A memory contains many memory cells, and each memory cell can hold a byte (addressed by byte). The location of each storage unit has a number, that is, the address, which is generally expressed in hexadecimal. The sum of the data that all storage units in a memory can store is called its storage capacity. Assume that the address code of a memory consists of 20-bit binary numbers (that is, 5-bit hexadecimal numbers), which can represent 2 to the 20th power, that is, 1M memory cell addresses. Each memory cell stores one byte, so the storage capacity of the memory is 1MB.

principle of operation

Only the working principle of dynamic memory (DRAM) is introduced here.

Each chip of dynamic memory has only one input data line and eight address pins. In order to form a 64K address, an address forming circuit must be specially designed between the system address bus and the chip address lead. The system address bus signal can be added to the pins of 8 addresses in time-sharing, and the memory cells in the chip are selected by the row latch, column latch and decoding circuits inside the chip, and the latch signal is also generated by the external address circuit. When reading data from a DRAM chip, the CPU first adds the row address to A0-A7, and then sends out a RAS latch signal, the falling edge of which latches the address in the chip. Then add the column address to A0-A7 of the chip, and then send the CAS latch signal, which also latches the column address in the chip on the falling edge of the signal. Then keep WE= 1, and the data will be output and saved within the validity period of CAS.

When data needs to be written into the chip, the row and column addresses lock the RAS and CAS in the chip, and then, WE is valid, and the data to be written is written into the selected memory cell. Because it is impossible for the capacitor to keep the charge unchanged for a long time, it is necessary to re-read each memory cell of the dynamic memory circuit periodically to keep the charge stable. This process is called dynamic memory refresh. The refresh of DRAM in PC/XT machine is realized by DMA. First, the counter 1 of the programmable timer 8253 is used to generate a DMA request at each 1⒌ 12μs, which is added to the 0 channel of the DMA controller. When the request of channel 0 of the DMA controller is responded, the DMA controller sends a refresh address signal to read the dynamic memory and refreshes one line at a time.

major function

Memory mainly stores programs and data. Just like the warehouse where goods are stored, people usually number the goods in the warehouse to facilitate access and leave access channels.

The memory consists of memory bank, address decoder, read-write control circuit, address bus and data bus. The memory that can directly and randomly access instructions and data by the central processing unit is called the main memory, and the large-capacity memory such as magnetic disk, magnetic tape and optical disk is called the external memory (or auxiliary memory). Memory is the storage device of computer, and its main function is to store programs and data. Program is the basis of computer operation, and data is the object of computer operation. Both programs and data are represented in binary form in memory, collectively referred to as information. In a computer, the memory capacity is in bytes (abbreviated as B), and a byte consists of eight binary bits. In addition to bytes, there are KB, MB, GB and TB (which can be abbreviated as K, M, G and T respectively, for example, 128MB can be abbreviated as 128M). In which: 1KB= 1024B, 1MB= 1024KB, 1GB= 1024MB,1TB =/kloc-0. Memory is generally divided into main memory (memory) and auxiliary memory (external memory). The composition of the memory is shown in the figure. Random Access Memory (RAM) Main Memory (Internal Memory) Read Only Memory (ROM) Memory Hard Disk Auxiliary Memory (External Memory) Floppy Disk Other Figures 1. 1.2 Memory Composition. The main memory is directly connected to the CPU and stores the currently running programs and related data. The access speed is fast, but the price is expensive and the capacity cannot be too large. At present, the memory configuration of microcomputer is generally 65438+. Main memory is divided into random access memory (RAM) and read-only memory (ROM) according to its working mode. Data in random access memory (RAM) can be read or written randomly, and it is used to store programs and related data transmitted from external memory and data sent from CPU. What people usually say about memory actually refers to RAM.

Classification by storage media

(1) semiconductor memory A memory composed of semiconductor devices is called a semiconductor memory; Features: high integration, large capacity, small volume, fast access, low power consumption, low price and simple maintenance. Mainly divided into two categories: bipolar memory: TTL type and ECL type. Metal oxide semiconductor memory (MOS memory for short): static MOS memory and dynamic MOS memory.

(2) Magnetic Surface Memory A memory made of magnetic materials is called magnetic surface memory, or magnetic memory for short. It includes disk storage, tape storage and so on. Features: large volume, low degree of production automation and slow access speed, but the storage capacity is much larger than that of semiconductor memory and it is not easy to lose.

(3) The laser stored information is stored on the disk surface in the form of a notch, and the disk surface is irradiated with a laser beam, and the information is read by using the different reflectivity of the disk surface. Optical discs can be divided into three types: CD-ROM, WORM and MOD.

2. Classification by access method

(1) random access memory (RAM): If the contents of any storage unit in the memory can be accessed randomly, and the access time is independent of the physical location of the storage unit, this memory is called random access memory (RAM). RAM is mainly used to store various input and output programs, data, intermediate operation results, information exchanged with the outside world and for stacking. Random access memory mainly acts as cache memory and main memory.

(2) Serial Access Memory (SAS): If the memory can only be accessed in a certain order, that is, the access time is related to the physical location of the storage unit, then this memory is called serial access memory. Serial memory can be divided into sequential access memory (SAM) and direct access memory (DAM). A sequential access memory is a complete serial access memory, such as a magnetic tape, in which information is written (or read) in a sequential manner from the beginning of the storage medium; Direct access memory is a part of serial access memory, such as disk memory, which is between sequential access and random access.

(3) Read-only memory (ROM): Read-only memory is a memory whose contents can only be read but not written, that is, a memory written once in advance. Usually used to store fixed information. Such as memory commonly used for microprogram control. At present, there are erasable read-only memories. Common ones are mask read-only memory (MROM), erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM). ROM is simpler, more integrated and cheaper than RAM, and it is a non-volatile memory. Computers often put some management, monitoring programs and mature user programs in ROM.

3. Classify information according to its preservability

Non-permanent memory: memory where information disappears after power failure, such as semiconductor read-write memory RAM.

Memory with permanent memory: Memory that can retain information after power failure, such as memory made of magnetic materials, semiconductor ROM, etc.

4. According to the role in the computer system

According to the function of memory in computer system, it can be divided into main memory, auxiliary memory, cache memory, control memory and so on. In order to solve the contradiction between large capacity, high speed and low cost, multilevel memory architecture is usually adopted at present, that is, cache, main memory and external memory are used.

Ability influence

Operations such as switching from a write command to a read command, accessing an address at a specific time, and refreshing data all require the data bus to remain dormant for a specific period of time, so that the memory channel cannot be fully utilized. In addition, wide parallel bus and DRAM kernel prefetching often lead to unnecessarily large amounts of data access. The useful data that the memory controller can access in a specified period of time is called effective data rate, which largely depends on the specific application of the system. The effective data rate varies with time and is usually lower than the peak data rate. In some systems, the effective data rate may drop below 10% of the peak rate.

Generally speaking, these systems benefit from changes in memory technology and can produce higher effective data rates. The CPU has a similar phenomenon. In recent years, companies such as AMD and TRANSMETA have pointed out that clock frequency is not the only factor when measuring the performance of CPU-based systems. Memory technology is very mature, and the peak rate and effective data rate may not match well than before. Although the peak rate is still one of the most important parameters of memory technology, other structural parameters can also greatly affect the performance of memory systems.

Parameters affecting effective data rate

There are several parameters that affect the effective data rate. One is to stop the data bus for several cycles. Among these parameters, bus conversion, line cycle time, CAS delay and RAS-to-CAS delay (tRCD) are the most important delay problems in the system structure.

Bus switching itself will cause a long stop time on the data channel. Take GDDR3 system as an example, it constantly writes data to the open page of memory. During this period, the effective data rate of the storage system is equal to its peak rate. However, it is assumed that the memory controller switches from reading to writing in 100 clock cycles. Since the conversion takes 6 clock cycles, the effective data rate is reduced to 94% of the peak rate. In this 100 clock cycle, if the memory controller switches the bus from writing to reading, more clock cycles will be lost. This storage technology needs 15 idle cycles when switching from writing to reading, which will further reduce the effective data rate to 79% of the peak rate. Table 1 gives similar calculation results of several high-performance memory technologies.

Obviously, all memory technologies are different. System designers who need a lot of bus conversion can choose more efficient technologies such as XDR, RDRAM or DDR2 to improve performance. On the other hand, if the system can divide the transaction into a long read-write sequence, then the bus conversion has the least impact on the effective bandwidth. However, other phenomena that increase latency, such as bank collision, will reduce the effective bandwidth and have a negative impact on performance.

DRAM technology requires opening a page or row of a library before accessing it. Once opened, different pages in the same library cannot be opened before the minimum cycle time, that is, the end of the production line cycle time (tRC). Different page accesses to open memory banks are called page misses, which may lead to delays associated with unsatisfied portions of any tRC interval. For libraries that are not open enough cycles to meet the tRC gap, page loss is called library conflict. TRC determines the delay time of bank collision, and the number of available banks on a given DRAM directly affects the frequency of bank collision.

Most memory technologies have four or eight banks and have tRC values in dozens of clock cycles. Under random load, a core with 8 libraries has fewer library conflicts than a core with 4 libraries. Although the interaction between tRC and library number is complex, its cumulative impact can be quantified in many ways.

Memory read transaction processing

Consider three simple memory read transactions. In the first case, the memory controller issues each transaction, which conflicts with the library generated by the previous transaction. The controller must wait a tRC time between opening a page and opening a subsequent page, which increases the maximum delay time related to page cycling. The effective data rate in this case depends largely on I/O and is mainly limited by DRAM core circuit. The maximum bank collision frequency reduces the effective bandwidth to 20% to 30% of the current peak of the highest-end memory technology.

In the second case, each transaction targets a randomly generated address. The probability of library conflict at this time depends on many factors, including the interaction between tRC and the number of libraries in the memory core. The smaller the tRC value, the faster the open page circulates and the smaller the loss caused by library conflict. In addition, the more banks in memory technology, the smaller the probability of random address access bank collision.

In the third case, each transaction is a page hit, and different column addresses are addressed in the open page. The controller does not need to access the closed page, allowing full use of the bus, thus obtaining the ideal situation that the effective data rate is equal to the peak rate.

The first and third cases involve simple calculation, and the random case is influenced by other characteristics, which are not included in DRAM or memory interface. Memory controller arbitration and queuing will greatly increase the frequency of bank conflicts, because transactions that do not cause conflicts are more likely to occur than those that do.

However, increasing the memory queue depth does not necessarily increase the relative effective data rate between different memory technologies. For example, even if the depth of the memory control queue is increased, the effective data rate of XDR is 20% higher than that of GDDR3. This increase is mainly because XDR has more libraries and lower tRC values. Generally speaking, shorter tRC intervals, more libraries and larger controller queues can produce higher effective bandwidth.

In fact, many efficiency restrictions are related to the granularity of row access. TRC constraint essentially requires the memory controller to access a certain amount of data from newly opened rows to ensure that the data pipeline remains full. In fact, in order to keep the data bus running uninterrupted, even if no extra data is needed, only a small amount of data needs to be read after opening a line.

Another major feature of reducing the effective bandwidth of a memory system is classified into the category of column access granularity, which specifies the amount of data that must be transferred for each read and write operation. On the contrary, the granularity of row access specifies how many separate read and write operations are required for each row activation (generally referring to CAS operation of each RAS). The granularity of column access has a great influence on the effective data rate and is not easy to quantify. Because it specifies the minimum amount of data that needs to be transferred in a read or write operation, the granularity of column access brings problems to those systems that only need a small amount of data at a time. For example, an access granularity system of 16 bytes needs 8 bytes from two columns, and a total of ***32 bytes must be read to access two locations. Because only 16 bytes out of 32 bytes are needed, the effective data rate of the system is reduced to 50% of the peak rate. Two structural parameters, bus bandwidth and pulse time length, define the access granularity of the storage system.

Bus bandwidth refers to the number of data lines connecting the memory controller and the memory device. It sets the minimum access granularity, because each data line must pass at least one data bit for a given memory transaction. The pulse duration specifies the number of bits that each data line must transmit for a given transaction. A storage technology, in each transaction, each data line only transmits one data bit, and its pulse time length is 1. The total granularity of column access is simple: column access granularity = bus width × pulse time length.

Many system architectures can only increase the available bandwidth of the storage system by increasing the bandwidth of DRAM devices and storage buses. After all, if four connections with 400MHz data rate can achieve the total peak bandwidth of 1.6GHz, then eight connections will get 3.2GHz. Adding a DRAM device will increase the number of wires on the circuit board and the number of pins of ASIC, and the total peak bandwidth will be doubled accordingly.

First of all, architects want to make full use of peak bandwidth, which has reached the maximum they can achieve by physically designing the memory bus. Graphics controllers with 256-bit or even 5 12-bit memory buses are not uncommon. The controller needs 1 1,000 pins or more. Packaging designers, ASIC bottom planning engineers and circuit board design engineers can't find a silicon chip area to route so many signals in a cheap and commercially feasible way. Due to the limitation of column access granularity, only increasing the bus width to obtain higher peak data rate will lead to the decrease of effective bandwidth.

Assuming that the pulse time length of a specific storage technology is equal to 1, the access granularity of a 5 12-bit-wide system for one memory processing is 5 12 bits (or 64 bytes). If the controller only needs a short piece of data, the remaining data will be wasted, thus reducing the effective data rate of the system. For example, a controller that only needs to store 32 bytes of system data will waste the remaining 32 bytes, resulting in an effective data rate equal to 50% of the peak rate. These calculations assume that the pulse duration is 1. With the increase of data rate of memory interface, the minimum pulse time length of most new technologies is greater than 1.

Selection skill

The type of memory will determine the operation and performance of the whole embedded system, so the selection of memory is a very important decision. Whether the system is powered by battery or commercial power, the application requirements will determine the type of memory (volatile or nonvolatile) and the purpose of use (storing code, data or both). In addition, the size and cost of memory are also important factors to be considered in the selection process. For smaller systems, the microcontroller's own memory may meet the system requirements, while larger systems may need additional external memory. When selecting memory type for embedded system, some design parameters need to be considered, including microcontroller selection, voltage range, battery life, reading and writing speed, memory size, memory characteristics, erase/write durability and total system cost.

Basic principles to be followed when selecting memory.

1, internal memory and external memory

Generally speaking, after determining the storage space required for storing program code and data, the design engineer will decide whether to use internal memory or external memory. Generally speaking, internal memory is the most cost-effective but inflexible, so design engineers must determine whether the demand for memory will increase in the future and whether there is some way to upgrade to a microcontroller with a larger code space. Considering the cost, people usually choose a microcontroller with the minimum storage capacity that can meet the application requirements, so they must be very careful when predicting the code size, because the increase of the code size may require the replacement of the microcontroller. At present, there are various sizes of external memory devices on the market, so it is easy for us to adapt to the increase of code size by increasing memory. Sometimes this means replacing the existing memory with a memory with the same package size but larger capacity, or adding memory to the bus. Even if the microcontroller has internal memory, it can meet the system's demand for non-volatile memory by adding external serial EEPROM or flash memory.

2. Boot memory

In larger microcontroller systems or processor-based systems, design engineers can use boot code for initialization. The application itself usually decides whether it needs boot code and special boot memory. For example, if there is no external addressing bus or serial boot interface, internal memory is usually used without special boot devices. However, in some systems without internal program memory, initialization is a part of operating code, so all codes will reside in the same external program memory. Some microcontrollers have both internal memory and external addressing bus. In this case, the boot code will reside in the internal memory and the operation code will reside in the external memory. This may be the safest method, because there will be no accidental modification of the boot code when changing the operation code. In all cases, the boot memory must be nonvolatile.

Any type of memory can be used to meet the requirements of embedded system, but terminal application and total cost requirements are usually the main factors that affect our decision. Sometimes, combining several types of memories can better meet the requirements of application systems. For example, some PDA designs use volatile memory and nonvolatile memory as program memory and data memory. Permanent programs are stored in nonvolatile ROM, while programs and data downloaded by users are stored in volatile DRAM with battery support. No matter which type of memory is selected, the design engineer must carefully consider various design factors before determining the memory to be used in the final application system.