What is the general written test for East Normal University enrollment?

Analog circuit 1, Kirchhoff theorem content (Shilan microelectronics) Kirchhoff current law law of charge conservation law, that is, the charge flowing into the circuit node is equal to the charge flowing into the same node. Kirchhoff's law of voltage and law of conservation of energy, that is, the line voltage is zero. 2. Formula of plate capacitance (C=εS/4πkd) (unknown) 3. Basic curve characteristics of triode (unknown) 4. Describe the concept of feedback circuit and enumerate its applications. Advantages of negative feedback (reducing amplifier gain sensitivity, changing input resistance, improving amplifier linear and nonlinear distortion effect, and expanding amplifier passband self-adjustment function) (unknown) 6. What is the purpose of frequency compensation of amplifier circuit (Slan Microelectronics) 7. Frequency response: how to change the frequency response curve (unknown) 8. Check the phase compensation of the operational amplifier and draw a compensation Bode diagram (concave and convex) 9. The advantages and disadvantages of basic amplifier circuits (voltage amplifier, current amplifier, mutual inductor and transimpedance amplifier) are widely used. The original (unknown) differential structure is 10, and difference channel tells it the output voltage Y+Y-. Find the * * * modulus differential modulus (unknown) 1 1, draw two input tubes (concave and convex) of the differential amplifier 12, draw the schematic diagram of the addition, subtraction, differential and product operation circuit of the operational amplifier and draw the transistor-level operational amplifier circuit (Shi Lan Microelectronics) 13, and use the operational amplifier group 65433. Give a simple circuit an analysis of output voltage characteristics (product circuit) and find a point at the output (15, resistance r, capacitance c, series input voltage r C, voltage c, voltage r, voltage r, voltage r, etc. ) and determine the input voltage spectrum of two circuits, such as high-pass filter and low-pass filter RC; Q, clockdelay, write the expression (VIA 2003. 1 1.06 written test) 18, The advantages and disadvantages of static and state time series simulation (via 2003.6543438+010.06 written test) and how to improve the timing (VIA 2003.654438+065. 463663620) are discussed. Find the critical path for each gate-level diagram and the input to make the output depend on the critical path 2 1 simplify the Karnaugh of the logic plane digital circuit. Trigger and so on (unknown) Karnaugh map writing logic expression makes (via 2003.11.06 sea written test questions) 23, simplification F (A, b, c, D) = M (1, 3,415). Please show the CMOS inverter Schmatic. Layout and its cross section with Pwell process. Draw its transfer curve (Vout-Vin) and explain the PMOS and NMOS working areas of each section of the transfer curve. (Test the circuit design by pen-Beijing -03. 1 1.09) 25. To design a CMOS inverter with balanced rise and fall time, please define the rationalization of channel widths of PMOS and NMOS and explain? 26. The P-tube width ratio of standard inverter is higher than the N-tube width ratio (Shi Lan Microelectronics Company) 27. A two-input NAND gate (Yangzhi Electric Written Test) 28 is established by using mos transistor. Please draw the transistor-level schematic diagram of cmos 2 input AND gate and explain which input responds faster to the rising edge of the output. (Less Delay ti M e) (Circuit Design-Beijing -03. 1 1.09) 29. Drawing NOT, NAND, NOR symbol truth table transistor-level circuit (Infineon written test) 30. Drawing CMOS pictures, choose one mux gate (via 2003.1/KLOC). Using binary muxinv to realize XOR (Philips-Tang written test) 32, drawing Y and using logic cmos circuit 34 to realize ab+cd (Philips-Tang written test). Draw CMOS circuit to realize transistor-level circuit diagram of Y=A*B+C(D+E) (Shi Lan Microelectronics) 35. Use 1 to realize F(x, y) from four choices. Z)=xz+yz' (unknown) 36. Use a few NAND gates to realize the expression f = xxxx+xxxx+xxxx (practical simplification) 37. The expression is simplified by NOT and NAND, and the diagram of NOR group draws the waveforms of each point (Infineon written test) 38, and realizes logic (A XOR B)OR (C and D) according to the input waveform. Please select the logic type and explain1) inv2) and 3) or 4) NAND 5) nor 6) XOR Answer: NAND (unknown) 39, designing full adder (China) 40 with NAND gate, etc. The similarities and differences between the two circuits (Hua 4 1) are analyzed, and the A-input B waveform (Shi Lan Microelectronics) 42, A, B, C, D, E, several inputs and several F(A, B, C, D, E 1 input/Kloc) is realized with a simple circuit. Otherwise F0) use NAND gate to realize infinite input number (unknown) 43, use waveform to represent D flip-flop function (intelligent electric written test) 44, use transmission gate inverter to construct edge flip-flop (intelligent electric written test) 45, use logic to draw D flip-flop (VIA 2003.65438) to draw the circuit layout of CMOSD latch (unknown) 48, and distinguish D flip-flop D latch (Xintai hardware interview) 49. Briefly describe the similarities and differences of latchfilp-flop (unknown) 50, the conceptual differences of LATCHDFF (unknown) 5 1, and the differences between latches and registers. Line-level description of latch (Nanshan Bridge) 52. Make a two-phase circuit with D flip-flop and find the state diagram (China) 53. Please draw a logic circuit for frequency doubling with D flip-flop (Hanwang written test) 54. Use D flip-flop and NOR dual-frequency circuit (Eastcom written test) 55. How many flip-flop circuits are needed? (Intel) 16 frequency 56, design 1 bit adder with filp-floplogic-gate, input carry to the current stage, output carry to the next stage. (unknown) 57, using D flip-flop to do quaternary counting (China) 58, realizing N-bit Johnson counter, N=5 (Nanshan Bridge) 59, designing preset initial value 7-ary cycle counter 15-ary (Shi Lan Microelectronics) 60, designing digital circuit (unknown) 6 1 using Verilog/VHDL counter. Input clk input reset; Enter [7: 0] d; Output [7: 0] q; reg[7:0]q； Always @ (posedgclk or posedgeset) if (reset) q <; = 0; else q & lt= d； Endmodule 63, which uses D flip-flop to realize dual-frequency Verilog description (Hanwang written test) module divide2( clk, clk_o, RESET); Input clk, reset; Output clk _ o；; Wires come in; Sign out; If (reset) out <: = 0; Else out<= in assignment in = ~ out assignment clk _ o = outEndmodule 64. The more important the modern electrical design of programming logic devices is: a) What are the known programming logic devices? B) Describe 8-bit D flip-flop logic with VHDL or VERILOG and ABLE (written test in Hanwang). Palpldcplfdfpga module DFF8 (CLK, reset, d, q); Input clk input reset; Enter d; Output q; reg q； Always @ (posedgclk or posedgeset) if (reset) q <; = 0; else q & lt= d； Endmodule 65, please use HDL to describe four-bit full adder, five-frequency circuit (Shi Lan Microelectronics) 66, use verilog or VHDL to write segment code to realize 10 decimal counter (unknown) 67, use VERILOG or VHDL to write segment code to eliminate burr (unknown) 68, and use VERILOG to realize the topic of state machine (the drawing of state machine is poor and easy to be misunderstood) (via 2003 The lottery state machine accepts 125 yuan to sell newspapers, and each newspaper 5 yuan (Yangzhi written test) 7 1. (verilog programming language should meet the fpga design requirements () 72. There are two kinds of coins designed from beverage vending machines: beverage 10 and change: (1) draw fsm (finite state machine); (2) verilog programming language should meet the design requirements of fpga; (3) Design engineering tools and design process (unknown) 73. Draw the test 100 10 string state diagram, and verilog (via) 74, FSM1010/sequence detection module (Nanshan Bridge) A input terminal B input terminal A continuous input1/. Then enter 1 in B, otherwise 0 cases A: 0000005438+000100100000000100000010000000, please draw the state machine; ; Please use RTL to describe its state machine (unknown) 3~5v, verilog/vddl detection stream specific string (state written by state machine) (Philips-Tang written test) 76, verilog/vhdl writing fifo controller (including full and half-full signals) (Philips-Tang written test) 77. At present, users need an integrated circuit product, which requires the product to realize its functions: y=lnx. Suppose the company takes over the project and gives it to the product design. Talk about the whole design process of the product (Shi Lan Microelectronics) 78. The difference between sramfalsh memory and dram (interview with Xintai hardware) 79. Seek the schematic diagram of single-tube DRAM (Yang Songhua, Feng Maoguan, author of Digital Electrical Technology Foundation, Xidian Edition, page 205, figure 9- 14b). Keep in mind the problem of increasing the total refresh time (lowering the temperature, (Infineon written test) 80. Please draw a schematic diagram of China MONSRAM cell with 6 translators. Point (VIA pen test circuit design-Beijing-03.11.09) 81,nouns: sram, ssram, sdram nouns IRQ, BIOS, USB, VHDL, SDR IRQ: interrupt request BIOS: basic input and output system USB: universal serial bus VHDL: Foreign abbreviations and PCI, ECC, DDR, interrupt, pipeline IRQ, BIOS, USB, VHDL, VLSI VCO (Voltage Controlled Oscillator) RAM (State Random Access Memory) FIR IIR DFT (Discrete Fourier Transform). Or text ratio comparison: a. quantization error B. straight graph C. white balance _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _