CPU chip independently developed by China and its performance

/view/3625.htm Loongson-1, Loongson-1 CPU IP core is a 32-bit processor core with the characteristics of both general-purpose and embedded CPU. It adopts an instruction set similar to MIPS III, and has a seven-stage pipeline, a 32-bit integer unit and a 64-bit floating-point unit. The Loongson-1 CPU IP core is highly flexible and configurable, which facilitates the integration of various standard interfaces. Figure 1 shows the configurable structure of Godson-1 CPU IP core, in which the dotted line indicates that users can choose and configure according to their own needs, thus customizing the processor structure that is most suitable for users' applications. The main configurable modules include: floating-point component, multimedia component, memory management, cache and coprocessor interface. The floating-point components are fully compatible with MIPS floating-point instruction set, and the floating-point components and their related system software fully meet the binary floating-point operation standard of ANSI/IEEE 754- 1985. Floating-point components mainly include floating-point ALU components and floating-point multiplication/division components, and users can choose whether to add them according to their actual applications. Media components reuse the format fields and floating-point register files of MIPS floating-point instructions, and the media instruction set basically corresponds to various operations of Intel SSE media instruction set. The memory management unit has three working modes, namely, standard mode, direct mapping mode and no mapping mode. In the standard mode, TLB is divided into ITLB and DTLB, and each part consists of 48 page table entries. It also supports mapping and non-mapping conversion methods from virtual addresses to physical addresses. TLB can also be mapped directly without using CAM and RAM to reduce the area. In unmapped mode, TLB can even be removed, and direct SRAM can be used to access memory. The cache of Godson-1 CPU IP core is divided into instruction cache and data cache, which are independently configured, with 4K as one channel and can be configured as 4, 2 and 0 channels. Users can determine the size of the required cache according to the needs of the application, or even do not use the cache. The coprocessor interface provides an effective interface for external coprocessors. Godson-1 CPU IP core provides two sets of configurable processor bus interfaces: AMBA interface and Harvard SRAM interface. Godson-2, the Godson-2 CPU, adopts an advanced four-issue superscalar pipeline structure, with an on-chip first-level instruction and data cache of 64KB each, and an off-chip second-level cache of 8MB. The highest frequency is 1000MHz, and the power consumption is 3-5 watts, which is far lower than that of similar chips abroad. The measured performance of its SPEC CPU2000 test program is 1. Godson 3 is in the pre-research. Although Loongson 2 is popular, Loongson 3 is also in pre-research. It is reported that "Godson 3" will be a multi-core processor, or at least a quad-core product, and a coprocessor dedicated to Java programs will be added to improve the execution efficiency of Java programs and instruction cache tracking technology in Linux environment. "Godson 3" will eventually achieve an internal peak calculation speed of 5-1000 billion times per second.