Five trends to promote the development of semiconductor technology

In the past few decades, the growth of the global semiconductor industry is mainly driven by the demand for cutting-edge electronic devices such as desktop computers, notebook computers and wireless communication products, and the rise of cloud computing. These increases will continue to develop new applications for the high-performance computing market.

First of all, 5G will increase the amount of data exponentially. We need more and more servers to process and store these data. In 2020, Yole reported that the compound annual growth rate of high-end CPU and GPU in these server cores is expected to reach 29%. They will support a large number of data center applications such as supercomputing and high-performance computing services. Driven by emerging applications such as cloud games and artificial intelligence, GPU is expected to achieve faster growth. For example, in March 2020, Internet traffic increased by nearly 50%, and the commercial Internet data exchange in Frankfurt set a new world record of data throughput exceeding 9. 1 terabit per second.

The second main driver is mobile SOC, a smart phone chip. Although the growth of this market segment is not so fast, in the chip field with limited scale, the demand for more functions of these SoCs will promote further technological innovation.

In addition to the traditional dimension expansion of logic, memory and 3D interconnection, these emerging applications will need to take advantage of cross-domain innovation. This requires the adoption of new modules, new materials and architectural changes at the device, block and SoC levels to achieve system-level benefits. We summarize these innovations into five development trends of semiconductor technology.

Trend 1: Moore's law is still useful, which will extend the life of semiconductor technology by 8 to 10 years …

In the next 8 to 10 years, the density scaling of CMOS transistors will roughly follow Moore's law. This will mainly realize the scaling of logic standard cells through EUV mode and the introduction of new device architecture.

Extreme ultraviolet (EUV) lithography technology is introduced into the 7 nm technology node, which can design some of the most critical chip structures in a single exposure step. Beyond the 5 nm technology node (that is, when the metal spacing behind the critical line (BEOL) is below 28-30 nm), multimode EUV lithography will inevitably increase the wafer cost. Finally, we hope that high NA)EUV lithography technology can be used in the most critical 1nm node layer in the industry. This technology pushes some of these layers back to single patterning, thus providing advantages in terms of cost, yield and cycle time.

The study of random defects by Imec is of great significance to the development of EUV lithography technology. Random printing failure refers to random, non-repetitive and isolated defects, such as microbridge, partial disconnection, contact loss or merger. Low dose radiation can be used to improve random defects, thus increasing yield and cost.

In order to speed up the introduction of high-na EUV, we are installing Attolab, which can test some key high-na EUV materials (such as mask absorbers and resistors) before the advent of high-na EUV tools. At present, Attolab has successfully completed the first stage of installation, and it is expected that there will be high NA EUV exposure in the next few months.

Besides the progress of EUV mask aligner technology, Moore's Law can't continue without the innovation of FEOL equipment architecture. Today, FinFET is the mainstream transistor architecture, and the most advanced node has two fins in the 6T standard cell. However, reducing the fin length to 5T standard cell will reduce the number of fins, and each device in the standard cell has only one fin, which will lead to a sharp decline in the performance per unit area of devices. Here, vertically stacked nanosheet transistors are considered as the next generation devices, which can use the space occupied by devices more effectively. Another key descaling booster is buried power supply rail (BPR). FEOL is buried in the chip instead of BEOL, and these BPR will release the interconnection resource routing.

Scaling the nanosheets to 2nm generation will be limited by n-to-p space constraints. Imec envisions Forksheet as the next generation device. By defining n- p space with dielectric walls, the trace height can be further adjusted. Contrary to the traditional HVH design, another standard cell architecture development that helps to improve wiring efficiency is the vertical-horizontal-vertical (VHV) design of metal wires. Finally, the standard cell is reduced to 4T by complementary field effect transistor (CFET), and then the third dimension at the cell level is fully utilized. Complementary field effect transistor folds n-type field effect transistor and p-type field effect transistor.

Trend 2: At a fixed power, the improvement of logic performance will slow down.

With the above innovations, we expect that the transistor density will follow the path of Moore's planning. However, under the fixed power supply, the performance improvement from node to node is called Denard scaling law. Denard's scaling law shows that as the transistor becomes smaller and smaller, its power density remains unchanged, so the use of power is proportional to the area; The magnitude of voltage and current is proportional to the length.

Researchers all over the world are looking for ways to make up for this slowdown and further improve chip performance. Due to the improved power distribution, the above-mentioned buried power traces are expected to provide performance improvement at the system level. In addition, imec also focuses on increasing stress for nanoplates and fork devices, and improving the contact resistance (MOL) of the center line.

Two-dimensional materials such as tungsten disulfide (WS2) are expected to improve the channel performance, because they have stronger gate length scalability than Si or SiGe. Among them, the 2d-based equipment architecture is very promising, including multiple stacked sheets, each of which is surrounded by a gate stack and contacted from the side. Simulation shows that these devices have better performance than nanoplates at 1 nanonodes or larger nodes. In order to further improve the driving current of these devices, we focus on improving the channel growth quality, adding dopants to these new materials and improving the contact resistance. We try to speed up the learning cycle of these devices by associating physical characteristics (such as growth quality) with electrical characteristics.

In addition to FEOL, congestion and BEOL RC delay, these have become important bottlenecks for performance improvement. In order to improve the path resistance, we are studying the mixed metallization of Ru or Mo. We expect that the semi-damascene metallization module can improve the resistance and capacitance of the close-packed metal layer at the same time. Semi-damascene can be used between lines (control capacitance increase) by direct mode and using air gap as dielectric.

Allow us to increase the aspect ratio of metal lines (to reduce the resistance). At the same time, we have chosen various alternative conductors, such as binary alloy, as a substitute for "good old" copper to further reduce the line resistance.

Trend 3:3D technology makes more heterogeneous integration possible.

In the industrial field, systems are built by heterogeneous integration using 2.5D or 3D connections. All these are helpful to solve the memory problem, add functions to the system limited by shape, or increase the output of large chip system. As the logical PPAC (performance-area-cost) slows down, the intelligent function partition of SoC can provide another zoom knob. A typical example is high bandwidth memory stack (HBM), which consists of stacked DRAM chips, which are directly connected to processor chips such as GPU or CPU through short interposer links. The most typical case is the inter-module stack on Intel Lakefield CPU and AMD 7 nm Epyc CPU. In the future, we hope to see more such heterogeneous SoCs, which is the best bridge to improve chip performance.

At imec, we have brought some benefits at the SoC level by making use of our innovations in different fields (such as logic, memory, 3D…… ...). In order to link technology with system-level performance, we have established a framework called S-EAT (for benchmarking advanced technologies). This framework can evaluate the impact of specific technologies on system-level performance. For example, can we benefit from 3D partition of on-chip memory with lower cache level? What will happen at the system level if SRAM is replaced by magnetic memory (MRAM)?

In order to divide these deeper cache levels, we need a high-density wafer-to-wafer stacking technology. We have developed wafer-wafer hybrid bonding with a spacing of 700 nm, and believe that in the near future, the progress of bonding technology will make it possible to synthesize bonds with a spacing of 500 nm.

Realize heterogeneous integration through three-dimensional integration technology. We developed a micro bump interconnection method based on sn, and the interconnection spacing was reduced to 7? M. This high-density connection makes full use of the potential of silicon via technology, which makes it possible to realize a higher 3D interconnection density of 16x between molds or between molds and silicon connectors. This greatly reduces the SoC area requirement of HBM I/O interface (from 6 mm2 to 1 mm2), and may shorten the interconnection length of HBM memory stack by 1 mm at most. The die can also be directly bonded to silicon by using mixed copper bonding. We are developing 3? M-pitch die-wafer hybrid bonding has high tolerance and placement accuracy.

As SoC becomes more and more heterogeneous, different functions (logic, memory, I/O interface, analog …) on the chip do not need to come from a single CMOS technology. It may be more beneficial to optimize the design cost and output by adopting different process technologies for different subsystems. This evolution can also meet the diversification and customization needs of more chips.

Trend 4: NAND and DRAM are pushed to the limit; Non-volatile memory is on the rise

The market forecast of memory chips shows that the memory in 2020 will be the same as that in 20 19-this change may be partly related to the slowdown of coronavirus pneumonia-19. After 202 1 year, this market is expected to start growing again. The emerging non-volatile memory market is expected to be dominated by: 50% compound annual growth rate is mainly driven by the demand of embedded magnetic random access memory (MRAM) and independent phase change memory (PCM).

NAND storage will continue to increase, and there may be no subversive architectural changes in the next few years. Today's most advanced NAND products have 128 storage capacity. Due to the bonding between wafers, more layers may be generated, so 3D expansion will continue. Imec realizes this road map by developing low-resistance word line metals such as ruthenium, studying backup storage media stack, increasing channel current and determining control pressure. We also focus on replacing planar logic transistors around NAND with more advanced FinFET devices. We are exploring 3D FeFET and new wurtzite materials as 3D NAND to replace high-end storage applications. As a substitute for traditional 3D NAND, we are evaluating the feasibility of new memory.

For DRAM, the scaling speed of cells is slow, and EUV lithography technology may need to improve the pattern. Samsung recently announced that EUV DRAM products will adopt 10n m( 1a) level. In addition to exploring the EUV lithography mode of key DRAM structures, imec also provides building blocks for real 3D DRAM solutions.

In the field of embedded memory, I have made great efforts to understand and eventually dismantle the so-called memory wall. How fast does the CPU access data from the cache based on DRAM or SRAM? When multiple CPU cores access the cache, how to ensure the consistency of the cache? What is the bottleneck limiting speed? We are studying various magnetic random access memories (MRAM), including spin transfer torque (STT)-MRAM, spin orbital torque (SOT)-MRAM and voltage-controlled magnetic anisotropy (VCMA)-MRAM, in order to possibly replace some traditional SRAM-based L 1, L2 and L3 caches (Figure 4). Each MRAM memory has its own advantages and challenges, and may help us overcome the memory bottleneck by improving the speed, power consumption and/or memory density. In order to further improve the density, we are actively studying the selector that can be combined with the magnetic tunnel junction, which is the core of MRAM.

Trend 5: The rise of marginal artificial intelligence chip industry

It is estimated that the marginal AI will increase by 100% in the next five years. Different from cloud-based artificial intelligence, the inference function is embedded in the Internet of Things endpoints (such as mobile phones and smart speakers) located at the edge of the network. IoT devices communicate wirelessly with servers that are relatively close to the edge. The server decides what data to send to the cloud server (usually data needed for less time-sensitive tasks, such as retraining) and what data to process on the edge server.

Compared with cloud-based AI (data needs to move back and forth from endpoints to cloud servers), edge AI can solve privacy problems more easily. It also provides the advantages of fast response and reduced workload of the cloud server. Imagine an automatic car that needs to make decisions based on artificial intelligence. Because decisions need to be made very quickly, the system can't wait for data to be transmitted to the server and back. Considering the power limitations of IOT devices that are usually powered by batteries, the inference engines in these IOT devices also need to be very energy-efficient.

Nowadays, commercial edge AI chips plus fast GPU or ASIC can achieve the computational efficiency of1-100 tops/w. For the realization of the Internet of Things, it will need higher efficiency. The goal of Imec is to prove that the reasoning efficiency is10.000 tops/w w.

By studying the architecture of analog memory computing, we are developing a different method. This method breaks the traditional Von Neumann computing mode and is based on sending data from memory to CPU (or GPU) for calculation. Using analog memory computing can save a lot of energy to move data back and forth. In 20 19, we demonstrated the analog memory computing unit based on SRAM (built-in 22nm FD-SOI technology) and realized the efficiency of1000tops/w. In order to further increase it to 10. 000 tops/W, we are studying non-volatile memory, such as memory based on SOT-MRAM, FeFET and IGZO.